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| M62465FP Dolby Pro Logic Surround REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Description The M62465FP is a single chip LSI supporting the Dolby Pro Logic surround. This LSI contains all functions necessary for Dolby Pro Logic surround. In addition, it has Digital Space Surround functions (Disco, Hall, Live mode etc.) and echo function for karaoke. Note: Use of this LSI requires the license of Dolby Laboratories Licensing Corporation Dolby and the double-D symbol are trademarks of Dolby Laboratories Licensing Corporation. San Francisco, CA94103-4813, USA. This device available only to licensees of Dolby Lab. Licensing and application information may be obtained from Dolby Lab. Features (Mode) * Upper compatible for M62460FP and less external parts than M62460FP. * Includes all functions requires for Dolby Pro Logic Surround. Adaptive Matrix. Noise Sequencer by digital noise source and switched capacitor filter. Center Mode Control (Wide/Normal/PHANTOM/OFF). Modified Dolby B Type Noise Reduction. 4ch/3ch Stereo Selectable. Digital Delay: 15.4, 20, 28.6 ms for Dolby Pro Logic Surround. * C/Sch Trimmer: 0 to -31 dB/1 dB Step. * Digital Space Surround Mode: Disco/Hall/Live mode and 5 delay time positions. * Digital Echo function for KARAOKE: (Short echo) Delay time = 147.5 ms, (Long echo) Delay time = 196.6 ms. * BY-PASS Mode: Input signal through output. System Block Diagram Lch IN Rch IN L+R 2 L-R 2 C R Center trim Surround trim C S Master volume control Adaptive matrix S Center/operating mode control Input autobalance control L R L Lch Rch CENTER SURROUND Digital noise sequencer 7 kHz LPF LPF-IN Modified S dolby B-NR NR-IN LPF-OUT MIC IN Digital delay MCU interface DATA SCK REQ REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 1 of 24 DELAY SIG OUT DELAY SIG IN FBIN SU 46 SFB 64 + - 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 45 44 MIX 43 42 41 VOL SU EC RLC6 65 66 Combinning networks Full wave rectifier BPF L-R VCA LOG difference amplifiers +9.2 dB S' +3.2 dB Dual-time constant and threshold switches MOS LLI LBPF 67 68 BPF L+R LPF Modified B-type NR decoder VOL OUT FBIN EC S' OUT DBIN DBC3 DBC2 DBC1 LPIN PSC4 PSC1 PSC5 PSC2 PSC6 PSC3 RLC8 RLC3 RLC7 RLC4 RLC1 RLC2 RLC5 40 LPF2 OUT 39 LPF2 IN2 38 LPF2 IN1 RLI RBPF 69 70 Selector 71 72 73 74 AVcc 75 Digital noise sequencer 37 D/A DA INT OUT LT RT LIN RIN HOLDC AVcc VREFA 76 IREF VREF + LCR Auto balance VCA Servo LRC Center mode control L+R 2 36 DA INT IN 16 K SRAM -6.0 dB ATT MIC 35 Logic DA CONT 34 A/D AD CONT Selector2 33 AD INT OUT 32 L-R 2 AD INT IN ATT -3.2 dB S' 31 LPF LPF1 OUT S Selector1 29 Selector3 LPF1 IN1 VREFG 77 78 79 1/2 Vcc 28 DELAY IN IREF REF OUT NSQ 80 27 MCU interface Trimmer Trimmer + - MIX OUT CLK DATA SCK REQ AGND DVdd Test CNT VREFD AVdd DVss AVss 26 VREFD 25 L R CT C ST S AVdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 2 of 24 Block Diagram LOUT ROUT COUT FILTER SMRO ST SOUT CT + VREFA + - + - +/- S 30 LPF1 IN2 TEST CNT XOUT SMRI MIC IN AGND DVdd M62465FP DATA Note: The function of pin No.1, 79, 80 is different from that of M62460FP. REQ DVss SCK CMC LO1 LO2 LO3 XIN AVss M62465FP Pin Arrangement M62465FP REF OUT 79 HOLDC VREFG VREFA RBPF RLC6 LBPF AVcc IREF NSQ 80 RIN RLI LIN LLI RT LT 78 77 76 75 74 73 72 71 70 69 68 67 66 65 FILTER LOUT ROUT CT COUT ST SOUT CMC SMRO SMRI AGND MIC IN DVdd TEST CNT DATA SCK REQ LO1 LO2 LO3 XIN XOUT DVss AVss RLC8 RLC3 RLC7 RLC4 RLC1 RLC2 RLC5 PSC4 PSC1 PSC5 PSC2 PSC6 PSC3 DBC3 DBC2 DBC1 LPIN DBIN S' OUT FBIN SU FBIN EC DELAY SIG OUT DELAY SIG IN VOL OUT 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVdd VREFD Outline: PRQP0080GB-A (80P6N-A) MIX OUT DELAY IN LPF1 IN1 LPF1 IN2 (Top view) LPF1 OUT AD INT IN AD INT OUT AD CONT DA CONT DA INT IN DA INT OUT LPF2 IN1 LPF2 IN2 LPF2 OUT Note: The function of pin No.1, 79, 80 is different from that of M62460FP. REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 3 of 24 M62465FP Pin Description No. 2 3 Symbol LOUT ROUT Function Lch output Rch output Voltage 4V Description Direct output R-/Lchannel when the operation mode is BYPASS. When the mode is 4channel, they output Dolby Pro Logic R-/Lchannel signals. No output any signals when the operation mode is center mode is OFF or set to PHANTOM. COUT is output from C. Trimmer. Equivalent Circuit VCC 2 3 4 CT Cch output 4V VCC 5 COUT Cch output 4 5 6 ST Sch output 4V This pin output surround signals. Output is selected from BNRout, Dout No output signal when the operation mode is 3STEREO/MUTE. SOUT is output from S. Trimmer. VCC 6 7 7 9 SOUT SMRO Sch output Amplifier output 4V This is a amplifier to control mixed level of surround output with external resistance. VCC 9 10 SMRI Amplifier input VCC 10 12 MIC IN MIC input 4V Microphone input with ECHO MODE VCC 12 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 4 of 24 M62465FP No. 14 Symbol TEST CNT Function TEST control Voltage 0 Description Fixed to GND 14 Equivalent Circuit buffer 15 DATA Serial data "DATA" input -- Input via serial data from MCU. 15 buffer 16 17 SCK REQ Serial data "SCK" input Serial data "REQ" input Port output 0 16 17 buffer 18 19 20 LO1 LO2 LO3 -- Open collector output pin (NPN Tr) 18 19 20 21 22 26 XIN XOUT VREFD Oscillator input Oscillator output Reference output -- Connect 4 MHz ceramic resonator 21 22 2.5 V 1/2 VCC output Connect a filter capacitor. 26 27 MIX OUT S, L+R, L-R and MIC output 4V Signal output precedent to delay generator. That is S, L+R, L-R and MIC output. VCC 27 28 DELAY IN Delay input 2.5 V This is s delay input. Please input by AC coupling. 28 40 41 LPF2 OUT VOL OUT Delay signal output Output of a delay volume 2.5 V Delay signal output 40 This is output of a delay volume that possible to control +3 dB to -. 41 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 5 of 24 M62465FP No. 42 Symbol DELAYSIG IN -- Function Voltage 4V Description Delay signal input to a mixing amplifier Equivalent Circuit VCC 42 43 DELAYSIG OUT Input from mixing amplifier 4V Delay signal output from a mixing amplifier VCC 43 44 45 FBIN EC FBIN SU Feedback signal input 4V Feedback signal input with ECHO MODE Feedback signal input with SURROUND MODE VCC 44 45 46 SOUT Sch output 4V Sorround channel output precedent to delay generator. Always outputs signals, irrespectiv of the operation mode (2-/3-/4channel) VCC 46 47 DBIN LPF output 4V This amplifier compornent 7 kHz-LPF with external resistances and capaciters. LPF output is conected to input of Modifide BNR. VCC 47 48 LPIN Negative input of LPF VCC 48 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 6 of 24 M62465FP No. 72 73 Symbol LIN RIN Function Lch input Rch input Voltage 4V Description Input of Lch and Rch that is non-inverted input type. Please pul-up to VREF by external resistances for DC bias. Equivalent Circuit VCC 72 73 70 71 LT RT Autobalance Lch output Autobalance Rch output 4V Autobalance output. VCC 70 71 76 VREFA Reference voltage input Reference voltage output -- 77 VREFG 4V It is a reference voltage input terminal to each circuit inside the IC. Reference voltage output. Voltage is the fixed at 4V. 76 VCC 77 1 FILTER New future of M62465FP 1/2VCC Auxiliary 1/2VCC reference generator. 1/2VCC The terminal which make a 1/2VCC voltage by the resistance. When it is used, a filter capacitor is connected. VCC 1 79 REFOUT New future of M62465FP 1/2VCC output Auxiliary 1/2VCC reference generator. 1/2VCC 1/2VCC voltage output. It is used to change reference voltage except 4V. VCC 79 80 NSQ New future of M62465FP Noise sequencer monitor 4V Noise sequencer monitor output. It is only for test. VCC 80 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 7 of 24 M62465FP Absolute Maximum Ratings (Ta = 25C, unless otherwise noted) Item Supply voltage Symbol VCC VDD Power dissipation Thermal derating Operating temperature Storage temperature Pd K Topr Tstg Ratings 10.5 6.5 1.37 13.7 -20 to +75 -40 to +125 Unit V V W mW/C C C Standard board Ta 25C Condition Thermal Derating 1.5 Power Dissipation Pd (W) 1.37 1.0 0.685 0.5 0 0 25 50 75 100 125 150 Ambient Temperature Ta (C) Note: Standard board board size: 70mm x 70mm board thickness: 1.6 mm board material: glass epoxy copper pattern: 18 m copper thickness: 0.25 mm (width) copper size: 30 mm (length/lead) Recommended Operating Condition Item Analog supply voltage Digital supply voltage OSC clock VCC VDD fck Symbol Min 8.0 4.5 -- Limits Typ 9.0 5.0 4 Max 10.0 5.5 -- Unit V V MHz Condition REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 8 of 24 M62465FP Electrical Characteristics (Decoder) (VCC = 9 V, VDD = 5 V, 0dB Reference = 300 mVrms/1 kHz at C-OUT unless otherwise noted. (Cch Trimmer = 0 dB)) Item Overall Circuit current Circuit current Reference voltage Input auto valance Capture range Error correction Adaptive matrix Output level accuracy relative to Cch Matrix rejection relative. Headroom Total harmonic Distortion Signal to noise ratio Symbol ICC IDD Vref CPR CER VOL MR HRAM THDAM SNAM Min -- -- 3.5 -- -- -0.5 25 15 -- -- 75 95 Peak noise NopAM Limits Typ 25 25 4.0 5 4 0 40 17 0.05 0.002 80 100 Max 50 50 4.5 -- -- 0.5 -- -- 0.2 0.05 -- -- Unit mA mA V dB dB dB dB dB % dB L, R, Sch out L, R, C, Sch out L, R, C, S out L, R, C, Sch out 4ch mode L, Rch out 2ch mode Rg = 0 , weighted CCIR/AMR 4ch mode L, Rch out 2ch mode Quiescent Quiescent Quiescent Conditions -- -- 0.3 mVp-p measurement time = 4ch mode 40ms -- -- 0.3 2ch mode Noise sequencer (0 dBd Reference is input at NR-IN when adjust to 0 dB (300 mVrms/100 Hz) at S out. Output noise level Vno -15 -12.5 -10 dB Vno Output level accuracy relative to Cch Output noise peak Vnop Modified B type noise reduction Voltage gain VGNR Decode response 1 DEC1 Decode response 2 DEC2 Decode response 3 DEC3 Decode response 4 DEC4 THDNR Total harmonic distortion Headroom HRNR Signal to noise ratio SNNR Peak noise NoPNR C, Sch trimmer Attenuation level: -12dB ATT-12dB Maximum attenuation ATTmax Trimmer step TS Surround (L+R, L-R) % dB dB mVp-p dB dB dB % dB Vin = 0 dBd, f = 1 kHz Rg = 0 weighted CCIR/AMR REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 9 of 24 M62465FP Electrical Characteristics (Digital Delay) (Ta = 25C, VCC = 9 V, VDD = 5 V, Vin = 200 mVrms, fck = 4 MHz unless otherwise noted) Item Digital delay Delay time Symbol Td Min 12.4 17.0 25.6 38.0 46.2 137.5 186.6 -3.0 -- -- -- -- -- -- -- 0.7 -- -- -- -- -- -- -- 0 -- Limits Typ 15.4 20.0 28.6 41.0 49.2 147.5 196.6 0 0.3 0.3 0.5 0.6 0.7 1.5 2.0 1.0 -92 -92 -92 -90 -90 -82 -77 3 -70 Max 18.4 23.0 31.6 44.0 52.2 157.5 206.6 3.0 0.6 0.6 1.0 1.2 1.4 3.0 4.0 -- -80 -80 -80 -75 -75 -67 -62 6 -60 Unit ms Conditions See delay time control (15/24) fordelay time setting. Input-output gain Output distortion Gv THD dB % 30 kHz LPF Td = 15.4 ms Td = 20.0 ms Td = 28.6 ms Td = 41.0 ms Td = 49.2 ms Td = 147.5 ms Td = 196.6 ms Maximum output voltage Output noise voltage Vomax No Vrms dBv 30kHz LPF, THD = 10% Td = 15.4 ms Rg = 620 , Vi = 0 mVrms, Td = 20.0 ms IHF-A Td = 28.6 ms Td = 41.0 ms Td = 49.2 ms Td = 147.5 ms Td = 196.6 ms Volume max Delay off mode, Volume min, IHF-A Delay volume (VOL OUT) Input-output gain Maximum attenuation Gv ATTmax dB dB REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 10 of 24 M62465FP Test Circuit Vi48 Vi44 Vi45 Vi42 Vo46 Vo41 Vo43 10 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 100 k 100 k 0.1 F 330 k 0.22 F 0.22 F 0.22 F 0.68 F 0.22 F 0.1 F 0.1 F 0.1 F 4.7 F 4.7 F 24 k 0.0056 F 0.022 F 0.022 F 0.047 F 0.047 F 0.047 F 64 SFB 0.1 F 63 VOL 62 61 60 59 58 57 56 55 MIX 680 pF Full wave rectifier LOG difference amplifiers Modified B-type NR decoder SU EC LPF MOS +9.2 dB Dual-time constant and threshold switches 15 k 66 47 k 7.5 k 0.1 F 0.1 F BPF 67 VCA S' +3.2 dB Combining networks 15 k 0.1 F 47 k 7.5 k 0.1 F 680 pF 68 BPF 69 LC R 79 80 Trimmer Trimmer MCU interface DATA SCK REQ + - CLK AGND DVdd Test CNT VREFD AVdd DVss AVss 26 25 + REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 11 of 24 70 Selector 71 MIC 22 k -6.0 dB ATT Logic A/D 16 K SRAM Vi72 10 F 10 F 22 F 72 73 L-R 2 Auto balance Center mode control VCA Selector2 L+R 2 Vi73 22 k Servo LRC 74 ATT -3.2 dB + +/- - +- S' S74 4.7 M LPF AVcc +9 V + 75 Selector1 AVcc VREFA S Selector3 S 76 220 F 77 78 100 k L 1 2 3 4 5 6 7 0.1 F R CT C ST S 8 9 10 10 k 10 k 11 12 13 14 15 15 16 16 17 17 + 10 F + + + + 10 F + 1 k Rout 10 F Lout 10 F Cout 10 F Sout 10 F + 1 F + 1 F 14 1 + - 65 + 24 k + Vo40 46 45 44 43 42 41 0.1 F 54 53 52 51 50 49 48 47 40 0.0018 F 39 0.01 F 38 37 0.068 F* L+R L-R D/A 36 0.1 F* + 35 34 33 0.068 F* 0.1 F* + + 32 31 0.0018 F + 100 F 30 0.01 F + 29 1 F 28 1 F Digital noise sequencer Vi28 27 22 F VREF IREF + Vo27 1/2 VCC Vo2 Vo3 Vo4 Vo5 Vo6 Vo7 AVdd +5 V 18 19 20 2 2 1 2 1 2 1 M 4 MHz 21 1 22 S21 1 2 23 24 Vi12 Vi10 27 pF 2 k 2 k 2 k S18 DVdd +5 V 18 19 20 DGND AGND (5 V) (5 V) Vi21 Note: The capacitors marked with * should be of relative precision 5% Max. Vo22 Vo18 Vo19 Vo20 M62465FP Digital Control Specifications (1) Data timing REQ t7 t2 t3 t4 t8 SCK t1 t5 t6 3 4 5 6 7 8 9 10 11 DATA 0 1 2 Notes: 1. SCK is disable when REQ is high. 2. REQ must turn to high after SCK pulse turn to high. Item SCK clock duration SCK "H" pulse width SCK "L" pulse width REQ hold time DATA setup time DATA hold time SCK setup time REQ "H" pulse width t1 t2 t3 t4 t5 t6 t7 t8 Symbol Min 2 0.8 0.8 1.6 0.8 0.8 0.8 1.6 Typ -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- Unit s s s s s s s s (2) Data Format Serial Data Format Data BIT4 BIT5 BIT6 BIT7 SELECTOR1 CENTER MODE MIX LO1 LO2 LO3 Sch. TRIMMER V2 V3 V4 SFB Address BIT10 BIT11 0 0 0 1 1 0 1 1 BIT0 BIT1 BIT2 BIT3 ADD/SUB NOISE SEQ SELECTOR2 SELECTOR3 Cch. TRIMMER S1 S2 S3 V1 BIT8 No use No use MOS BIT9 MIC (3) Decoder Address (BIT10, 11) = 0, 0 ADD/SUB Mode ADD SUB NOISE SEQ Mode OFF ON BIT1 0 1 Mode L C R S BIT2 0 0 1 1 BIT3 0 1 0 1 BIT0 0 1 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 12 of 24 M62465FP SELECTOR 1 Mode PRO LOGIC BY-PASS OTHER SUR L/R MUTE BIT4 0 0 1 1 CENTER MODE BIT6 0 0 1 1 BIT5 0 1 0 1 Mode WIDE NORMAL PHANTOM OFF BIT7 0 1 0 1 Address (BIT10, 11) = 0, 1 Mode S L+R L-R MIC SELECTOR 2 BIT0 0 0 1 1 SELECTOR 3 BIT2 0 0 1 1 Delay Mix Switch DMIXSW OFF ON LO (LOGIC DATA OUT) Open Collector Mode Output data "L" Output data "H" BIT5 (LO1) 0 1 BIT6 (LO2) 0 1 BIT7 (LO3) 0 1 BIT1 0 1 0 1 Mode BNR OUT D OUT 3STEREO/MUTE BIT3 0 1 0 1 BIT4 (MIX) 0 1 Remarks Mixing OFF Mixing ON Address (BIT10, 11) = 1, 0 DATA 0 1 BIT0 0 dB -1 dB Cch. TRIMMER BIT1 BIT2 0 dB 0 dB -2 dB -4 dB Sch. TRIMMER BIT6 BIT7 0 dB 0 dB -2 dB -4 dB BIT3 0 dB -8 dB BIT4 0 dB -16 dB DATA 0 1 BIT5 0 dB -1 dB BIT8 0 dB -8 dB BIT9 0 dB -16 dB REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 13 of 24 M62465FP Volume Code ATT(dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 BIT0(5) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BIT1(6) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT2(7) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C(S)ch. TRIMMER BIT3(8) BIT4(9) ATT(dB) 0 0 -16 0 0 -17 0 0 -18 0 0 -19 0 0 -20 0 0 -21 0 0 -22 0 0 -23 1 0 -24 1 0 -25 1 0 -26 1 0 -27 1 0 -28 1 0 -29 1 0 -30 1 0 -31 BIT0(5) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BIT1(6) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT2(7) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT3(8) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT4(9) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (4) Delay Address (BIT10, 11) = 1, 1 BIT0(S1) 0 0 0 0 1 1 1 1 BIT1(S2) 0 0 1 1 0 0 1 1 BIT2(S3) 0 1 0 1 0 1 0 1 Delay Time Control DELAY TIME (Sampling frequency) Delay LPF (Cut-off frequency) 15.4 ms (1 MHz) 7.0 kHz 20.0 ms (667 kHz) 28.6 ms (500 kHz) 41.0 ms (400 kHz) 49.2 ms (333 kHz) 147.5 ms (111.1 kHz) 3.0 kHz 196.6 ms (83.3 kHz) Delay off mode (clock off) Feedback Switch SFB SW OFF ON BIT7 (SFB) 0 1 Note: In surround mode only Remarks Feedback OFF Feedback ON Mode Selector BIT8 (MOS) 0 1 MODESEL SU line EC line REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 14 of 24 M62465FP BIT9 (MIC) 0 1 Note: Microphone Mixing Switch MICMIXSW OFF ON Remarks Mic mixing OFF Mic mixing ON 1. Settings in power up When power is turned on, data is setting in under table by power on reset circuit. DECODER Mode Settings ADD OFF PROLOGIC WIDE S BNR OUT "L" 0 dB, ATT (-) 0 dB, ATT (-) DELAY Mode Delay time control Volume control Feedback switch Mode selector Delay mix switch Microphone mixing switch Settings 20.0 ms - OFF SU line OFF OFF ADD/SUB Noise SEQ SELECTOR1 Center mode SELECTOR2 SELECTOR3 LO (LOGIC OUT) Cch. Trimmer Sch. Trimmer Notes: 2. The digital the noise sequencer stop when the clock is off. Volume Control BIT5 (V3) 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 BIT3 (V1) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BIT4 (V2) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 BIT6 (V4) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VOL Attenuation +3 dB 0 dB -2 dB -3 dB -4 dB -6 dB -8 dB -9 dB -10 dB -12 dB -15 dB - - - - - REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 15 of 24 Volume Level Selector Cch Trimmer Sch Trimmer 1 Pro Logic OFF OFF OFF S' BNROUT/ 3 Stereo Wide SU -- S' 2 3 Note VOL OFF (0 dB) Normal 0 to -31 dB 0 to -31 dB 1 dB/step 1 dB/step Delay VOL M62465FP Switch Condition Mode SUBMode Digital Delay Digital Center ADD/ Delay Delay Mode SUB MIX SW Mode Feedback MIC MIX Input Dolby Pro Logic Wide td = 15.4 ms, 20.0 ms, 28.6 ms Function Mode (Example) Normal Feedback level can be changed by output port control (see block diagram) REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 16 of 24 Phantom VOL ATT Other L-R SUR +3 dB DOUT OFF Phantom SUB 0 dB -2 dB -3 dB -4 dB L+R -6 dB -8 dB -9 dB -10 dB -12 dB -15 dB - Bypass MIC 3 Stereo OFF ADD ON EC OFF ON MIC S'/ BNROUT/ Wide/ ADD/ L+R/ 3 Stereo/ Normal/ SUB L-R DOUT Phantom ON/ OFF ADD OFF SU ON OFF (L-R) 2 (L+R) 2 * Pro Logic decoder function is alive. For example C/S trimmer can be available. -31 dB - Bypass S' 3 Stereo OFF ADD OFF SU OFF OFF S' Phantom Digital space surround Disco td = 20 ms Hall * Delay time can be set to 5 position (15.4, 20.0, 28.6, 41.0, td = 49.2 ms and 49.2 ms) Live td = 28.6 ms Option 5 step delay time (BW = 7 kHz, fck = 4 MHz) Karaoke/ echo Short echo td = 147.5 ms BW = 3 kHz Long echo td = 195.5 ms By-pass By-pass td = 20.0 ms M62465FP Function Block Diagram By-pass Plo logic Other mute Selector1 Lout Rout Noise sequencer Selector4 Input balance Lin Rin (L+R) 2 (L-R) 2 S' Adaptive matrix L R C Center mode control Wide normal phantom OFF C.Trimmer (0 to -31 dB) ADD/SUB Cout CT 3-stereo/mute Selector3 BNR OUT + - Selector2 MIC MIX Modified BNR DOUT MIC S.Trimmer (0 to -31 dB) Sout Dout MIC VREFA Feedback Delay mix SW MOS SU EC Digital delay MCU Interface VOL - + AVcc (+9 V) AGND LO1 LO2 LO3 GND Echo filter Surround filter 7 kHz LPF AVDD VDD (+5 V) 4 MHz REQ SCK DATA Block Name Input balance Noise sequencer Adaptive matrix Center mode control C.Trimmer, S.Trimmer Modified BNR ADD/SUB Selector1 Selector2 Selector3 Selector4 Digital delay Function Revises a level error between the input Lch and Rch for optimum decoder performance. A simple noise sequencer circuit adjustment of output level. Continuously analyze the two-channel matrixes audio input to determine the direction and relative magnitude of encoded sound fields. Possible to select 4-center mode position. (WIDE, NORMAL, PHANTOM, OFF) This is the level adjustment volume of Cch and Sch. (0 to -30 dB: 1 dB/step) This block restores the signal to its original spectrum while reducing noise and certain cross talk signals in a final stage of the surround chain. Select a positive phase signal or a negative phase signal with DIGITAL SPACE SURROUND MODE. This is a selective switch to select the output signal of Lout and Rout from BY-PASS, PRO LOGIC, OTHER SUR and MUTE. This is a selective switch to select the output signal of Sout from S, L+R, L-R and MIC. This is a selective switch to select the output signal of Sout from BNR out, Dout and 3STEREO/MUTE. This is a switch to connect a simple noise sequencer output to ADAPTIVE MATRIX stage for level adjustment. Make 7 kinds of delay signal s. (15.4 ms to196.6 ms) The delay function and CLK signal stop at the time of DELAY OFF MODE. This mode is for suppress bad effect of digital noise. This is a switch to select feedback mode (ON/OFF) for SURROUND MODE. This is a switch to select feedback signal from surround signal and echo signal. Control the ATT level of delay signal from 3 dB to - (12-step) This is a switch to mix microphone signal to a main signal (Lch, Rch) . This is a switch to select output or not a mixed signal to DOUT pin. Feedback Mode sel (MOS) VOL MIC MIX Delay mix SW REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 17 of 24 M62465FP Level Diagram Dolby Pro Logic Mode Sout Gv VCC = 9 V 3 dB 0 dB (300 mV) 9.2 dB 0 dB (300 mV) VCC = 9 V VDD = 5 V Vref = 4 V Vref = 4 V GND Lin Rin S' -6 dB Vref = 2.5 V Input balance Adaptive matrix ATT -3.2 dB Digital delay Modified BNR SOUT Lout, Rout, Cout Gv VCC = 9 V Vref = 4 V 0 dB (300 mV) 3 dB Cout GND Gv VCC = 9 V Vref = 4 V 0 dB (300 mV) Lout, Rout GND Cout Lout Rout Lin Rin Input balance Adaptive matrix Center mode control REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 18 of 24 M62465FP Digital Space Surround Mode Sout Gv 0 dB (300 mV) 3 dB 0 dB (300 mV) VCC = 9 V VDD = 5 V VCC = 9 V Vref = 4 V Vref = 4 V GND Vref = 2.5 V Lin Rin L+R 2 L-R 2 Selector2 ATT -3.2 dB Digital delay Selector3 SOUT Lout, Rout Gv VCC = 9 V Vref = 4 V 0 dB (300 mV) Lout, Rout GND Lin Rin Input balance Adaptive matrix Center mode control Lout Rout REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 19 of 24 M62465FP Auto Mute Function The IC carries out auto mute function at the time of powering up, delay time setting change, and cancelling delay off mode, in order to suppress shock noise that the digital delay may produce. * At power up * Transient noise common with power up occurs. Reset time Power up Freed from resetting Mute time Freed from muting Internal delay time setting * At delay time setting change Delay signal before change Delay signal after change Mute time Instruction to change delay time Freed from muting Internal delay time change * At canceling delay off mode Mute time Canceling delay off mode Freed from muting Mute time changes depending on set (or preset) delay time. Delay time 15.4 to 49.2 ms 147.5, 196.6 ms Mute time 123 ms 492 ms REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 20 of 24 M62465FP RA45 R47 R44 C44 C47 C41 R48 R45 C45 RA44 C48 C49 C55 C50 64 63 62 61 60 59 58 57 56 55 SFB C65 MIX C66 Full wave rectifier LOG difference amplifiers Modified B-type NR decoder Dual-time constant and threshold switches LPF RA66 66 MOS C67 R67 R66 BPF 67 +9.2 dB VCA C70 S' +3.2 dB 79 80 Trimmer Trimmer 220 k MCU interface DATA SCK REQ + - CLK AGND DVdd VREFD AVdd DVss AVss Test CNT 26 25 + REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 21 of 24 Combining networks C68 R68 R69 RA68 68 BPF 69 LC R L+R L-R C69 The example is fixed 4 V reference voltage type. C71 70 Selector 71 -6.0 dB ATT MIC R72 A/D 16 K SRAM Lin C74 72 73 L-R 2 Auto balance Center mode control VCA Selector2 L+R 2 Rin + C72 C73 Servo LRC R73 74 ATT -3.2 dB + +/- - S' +- R74 LPF AVcc +9 V 75 76 S Selector3 S R77 AVcc VREFA + 77 78 Application Example 1 (Upper compatible for M62460FP) Digital noise sequencer R78 10 F AVdd +5 V 0.0056 F L 1 C8 R 2 3 4 5 6 7 8 CT C ST S 9 R9 10 11 12 13 14 15 16 17 + C2 C3 C5 + + + R6 C12 47 F + + C6 MCU C21 + - 65 + + C64 C63 C62 C61 C60 C59 C58 C57 C56 C54 C53 C52 C51 R51 54 VOL 40 53 52 51 50 49 48 47 46 45 44 43 42 41 C40 SU D/A EC C39 39 C38 38 37 C36 36 C35 + Logic 35 C34 34 33 C32 + 32 31 C30 + 30 C29 C75 + 29 28 C27 Selector1 + (Example) Feedback Level Control VREF IREF + 27 C26 1/2 VCC Lout Rout Cout Sout C25 + 18 LO1 19 LO2 20 LO3 21 R21 22 R22 23 24 C22 4 MHz DGND DVdd +5 V MIC in Note: It's recommended to remove these external parts of M62460FP. (These external parts don't affect the function of M62465FP actually.) M62465FP RA45 R47 R44 C44 C47 C41 R48 R45 C45 RA44 C48 C49 C55 C50 64 63 62 61 60 59 58 57 56 55 Application Example 2 SFB C65 MIX C66 Full wave rectifier LOG difference amplifiers Modified B-type NR decoder Dual-time constant and threshold switches LPF RA66 66 MOS C67 R67 R66 BPF 67 +9.2 dB VCA 79 80 Trimmer Trimmer C79 + - MCU interface DATA SCK REQ CLK AGND DVdd VREFD AVdd DVss AVss Test CNT 26 25 + REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 22 of 24 S' +3.2 dB C70 C68 R68 R69 Combining networks RA68 68 BPF 69 LC R The example is 1/2VCC reference voltage type. L+R L-R C69 C71 70 Selector 71 -6.0 dB ATT MIC R72 A/D 16 K SRAM Lin C74 72 73 L-R 2 Auto balance Center mode control VCA Selector2 L+R 2 Rin + C72 C73 Servo LRC R73 74 ATT -3.2 dB + +/- - S' +- R74 LPF AVcc +9 V 75 76 S Selector3 S 77 R78 AVcc VREFA + (Example) Feedback Level Control + Logic Selector1 VREF IREF 78 + AVdd +5 V L 1 C8 R 2 3 4 5 6 7 8 CT C ST S 9 R9 10 11 12 13 14 15 16 17 + C2 C3 C5 + + + R6 C12 + + C6 MCU C21 + - 65 + + C64 C63 C62 C61 C60 C59 C58 C57 C56 C54 C53 C52 C51 R51 54 VOL 40 53 52 51 50 49 48 47 46 45 44 43 42 41 C40 SU D/A EC C39 39 C38 38 37 C36 36 C35 35 C34 34 33 C32 + 32 31 C30 + 30 C29 C75 + 29 28 C27 Digital noise sequencer 27 C26 1/2 VCC C1 C25 + 18 LO1 19 LO2 20 LO3 21 R21 22 R22 23 24 C22 4 MHz DGND Lout Rout Cout DVdd +5 V MIC in Sout M62465FP External Parts List Parts No. C1 C2 C3 C5 C6 C8 C12 C21 C22 C25 C26 C27 C29 C30 C32 C34 C35 C36 C38 C39 C40 C41 C44 C45 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 Values 47 10 10 10 10 0.1 1 27 27 100 22 1 0.01 0.0018 0.068 0.1 0.1 0.068 0.01 0.0018 0.1 0.1 1200 470 680 0.1 0.0056 0.047 0.68 0.22 0.22 4.7 4.7 0.22 0.22 0.1 0.047 0.047 0.1 0.1 0.022 0.022 Unit F F F F F F F pF pF F F F F F F F F F F F F F pF pF pF F F F F F F F F F F F F F F F F F Tol. Parts No. C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C77 C79 Values 0.1 680 0.1 680 0.1 0.1 0.1 10 10 22 100 220 220 Unit F pF F pF F F F F F F F F F Tol. 20% 5% 5% 5% 5% 5% 5% 10% 20% 5% 5% 5% 5% 5% 5% 5% 5% 5% 10% 5% 5% 10% 10% 10% 20% 20% 10% 10% 20% 5% 5% 20% 20% 5% 5% R6 R9 R21 R22 RA44 RA45 R44 R45 R47 R48 R51 R66 RA66 R67 R68 RA68 R69 R72 R73 R74 R78 10 20 1 1 51 51 Vol Vol 24 24 330 47 15 7.5 47 15 7.5 22 22 4.7 100 k k M k k k k k k k k k k k k k k M k 5% 5% 10% 5% 5% 5% 5% 5% 5% 10% 1% REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 23 of 24 M62465FP Package Dimensions JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g HD *1 D 41 64 65 40 ZE *2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. HE E 80 25 Reference Symbol Dimension in Millimeters 1 ZD 24 Index mark F c D E A2 HD HE A A1 bp c L Detail F *3 REJ03F0219-0201 Rev.2.01 Mar 31, 2008 Page 24 of 24 A1 e y bp e y ZD ZE L Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 0.8 1.0 0.4 0.6 0.8 A A2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 (c) 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2 |
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